Ultra Fast DMA

We provide vendor-independent FPGA architecture of Ultra Fast DMA module IP with easy integration to open-source NDK. The DMA is designed for more than 400 Gbps throughput and uses multi-channel architecture to support the distribution of data among individual CPU cores (also known as Receive Side Scaling or RSS). The data transfer architecture is highly flexible and supports various high-end FPGA families and PCIe bus configurations (up to PCIe Gen4 x32 or Gen5 x16). The DMA IP can utilize more than one PCI Endpoint block to scale the throughput over 100 Gbps and to achieve 200 and 400 Gbps. DMA comes with open-source Linux drivers for high-speed DMA transfers using the DPDK communication standard.

The graph above demonstrates the real throughput of the 400 Gbps DMA architecture achieved on the Intel Stratix 10 DX Development Kit. The same DMA engine can provide comparably high throughput for any Xilinx UltraScale+ or Intel Agilex devices. The NDK Linux driver allows you to control each RSS channel separately. The NDK driver also provides a user-friendly API to connect your application core directly to the DMA IP. It is also possible to handle DMA transfers through the standard DPDK drivers because NDK is supported in the DPDK upstream.

DMA demonstration

Want to test high throughput of our DMA module IP by your own? No problem! We have prepared demonstration for you: